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NB7L86M 2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Termination
The NB7L86M is a multi-function differential Logic Gate, which can be configured as an AND/NAND, OR/NOR, XOR/XNOR, or 2:1 MUX. This device is part of the GigaComm family of high performance Silicon Germanium products. The NB7L86M is an ultra-low jitter multi-logic gate with a maximum data rate of 12 Gb/s and input clock frequency of 8 GHz suitable for Data Communication Systems, Telecom Systems, Fiber Channel, and GigE applications. Differential inputs incorporate internal 50 W termination resistors and accept LVNECL (Negative ECL), LVPECL (Positive ECL), LVCMOS, LVTTL, CML, or LVDS. The differential 16 mA CML output provides matching internal 50 W termination, and 400 mV output swing when externally terminated 50 W to VCC. The device is housed in a low profile 3x3 mm 16-pin QFN package. Application notes, models, and support documentation are available on www.onsemi.com.
Features http://onsemi.com MARKING DIAGRAM*
16 1
QFN-16 MN SUFFIX CASE 485G
NB7L 86M ALYWG G
* * * * * * * * * * * *
A L Y W G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
Maximum Input Clock Frequency up to 8 GHz Maximum Input Data Rate up to 12 Gb/s Typical < 0.5 ps of RMS Clock Jitter < 10 ps of Data Dependent Jitter 30 ps Typical Rise and Fall Times 90 ps Typical Propagation Delay 2 ps Typical Within Device Skew Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V CML Output Level (400 mV Peak-to-Peak Output) Differential Output 50 W Internal Input and Output Termination Resistors Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP and SG Devices Pb-Free Packages are Available
VTD0 D0 D0 VTD0 50 W
*For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet.
Q 50 W 50 W Q
VTD1 D1 D1 VTD1
50 W 50 W SEL
50 W
VTSEL
SEL
Figure 1. Simplified Logic Diagram
(c) Semiconductor Components Industries, LLC, 2006
January, 2006 - Rev. 3
1
Publication Order Number: NB7L86M/D
NB7L86M
VTD0 D0 16 VCC SEL SEL VTSEL 1 2 NB7L86M 3 4 5 6 7 8 10 9 Q VCC 15 D0 VTD0 Exposed Pad (EP) 14 13 12 11 VEE Q
VTD1 D1
D1 VTD1
Figure 2. Pin Configuration (Top View) Table 1. PIN DESCRIPTION
Pin 1, 9 2 3 4 5 6 7 8 10 11 12 13 14 15 16 - Name VCC SEL SEL VTSEL VTD1 D1 D1 VTD1 Q Q VEE VTD0 D0 D0 VTD0 EP I/O Power Supply LVPECL, CML, LVCMOS, LVTTL, LVDS Input LVPECL, CML, LVCMOS, LVTTL, LVDS Input - - LVPECL, CML, LVCMOS, LVTTL, LVDS Input LVPECL, CML, LVCMOS, LVTTL, LVDS Input - CML Output CML Output Power Supply - LVPECL, CML, LVCMOS, LVTTL, LVDS Input LVPECL, CML, LVCMOS, LVTTL, LVDS Input - - Description Positive supply voltage. All VCC pins must be externally connected to power supply to guarantee proper operation. Inverted differential select logic input. Non-inverted differential select logic Input. Common internal 50 W termination pin for SEL/SEL. See Table 6. (Note 1) Internal 50 W termination pin for D1. See Table 6. (Note 1) Non-inverted differential clock/data input D1. (Note 1) Inverted differential clock/data input D1. (Note 1) Internal 50 W termination pin for D1. See Table 6. (Note 1) Non-inverted output with internal 50 W source termination resistor. (Note 2) Inverted output with internal 50 W source termination resistor. (Note 2) Negative supply voltage. All VEE pins must be externally connected to power supply to guarantee proper operation. Internal 50 W termination pin for D0. (Note 1) Non-inverted differential clock/data input D0. (Note 1) Non-inverted differential clock/data input D0. (Note 1) Internal 50 W termination pin for D0. (Note 1) Exposed Pad. Thermal pad on the package bottom must be attached to a heatsinking conduit to improve heat transfer. It is recommended to connect the EP to the lower potential (VEE).
1. In the differential configuration when the input termination pins (VTDx, VTDx, VTSEL) are connected to a common termination voltage or left open, and if no signal is applied on Dx, Dx, SEL and SEL then the device will be susceptible to self-oscillation. 2. CML output require 50 W receiver termination resistor to VCC for proper operation.
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NB7L86M
VTD0 VT or VBB VCC VTD0 VTD1 50 W D0 D0 50 W 50 W Q Q D1 D1 50 W 50 W 50 W VEE VCC SEL D0 0 0 0 0
Table 2. AND/NAND TRUTH TABLE (Note 3)
D1 0 0 1 1 b SEL 0 1 0 1 AND b Q 0 0 0 1
m
VTD1
RD
3. D0, D1, SEL are complementary of D0, D1, SEL unless specified otherwise.
VTSEL SEL
b
Figure 3. Configuration for AND/NAND Function
50 W D0 D0 50 W VTD1 VCC VT or VBB VTD1 50 W 50 W D1 D1 50 W 50 W Q Q
VTD0
m
VTD0
Table 3. OR/NOR TRUTH TABLE (Note 4)
m D0 0 0 1 1 D1 1 1 1 1 b SEL 0 1 0 1 m or b Q 0 1 1 1
4. D0, D1, SEL are complementary of D0, D1, SEL unless specified otherwise.
VTSEL SEL
b
SEL
Figure 4. Configuration for OR/NOR Function
VTD0
50 W D0 D0 50 W Q Q D1 D1
m
VTD0
Table 4. XOR/XNOR TRUTH TABLE (Note 5)
m D0 0 0 1 50 W 1 D1 1 1 0 0 b SEL 0 1 0 1 m XOR b Q 0 1 1 0
VTD1
50 W
VTD1
50 W
50 W
VTSEL SEL
5. D0, D1, SEL are complementary of D0, D1, SEL unless specified otherwise. SEL
b
Figure 5. Configuration for XOR/XNOR Function
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NB7L86M
VTD0 D0 D0 VTD0 50 W VTD1 D1 D1 VTD1 50 W 50 W 50 W 50 W Q Q 50 W
Table 5. 2:1 MUX TRUTH TABLE (Note 6)
SEL 1 0 Q D1 D0
6. D0, D1, SEL are complementary of D0, D1, SEL unless specified otherwise.
SEL
VTSEL
SEL
Figure 6. Configuration for 2:1 MUX Function
Table 6. ATTRIBUTES
Characteristics ESD Protection Human Body Model Machine Model Charged Device Model Pb Pkg QFN-16 Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 7. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. Oxygen Index: 28 to 34 Level 1 Value > 1500 V > 50 V > 500 V Pb-Free Pkg Level 1
Moisture Sensitivity (Note 7)
UL 94 V-0 @ 0.125 in 400
Table 7. MAXIMUM RATINGS
Symbol VCC VI VINPP IIN Iout TA Tstg qJA qJC Tsol Parameter Positive Power Supply Input Voltage Differential Input Voltage |D - D| Input Current Through RT (50 W Resistor) Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 8) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm 2S2P (Note 8) QFN-16 QFN-16 QFN-16 Condition 1 VEE = 0 V VEE = 0 V VCC - VEE VCC - VEE < Continuous Surge Continuous Surge QFN-16 2.8 V 2.8 V VEE VI VCC Condition 2 Rating 3.6 3.6 2.8 |VCC - VEE| 25 50 25 50 -40 to +85 -65 to +150 42 36 3 to 4 265 265 Units V V V V mA mA mA mA C C C/W C/W C/W C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 8. JEDEC standard multilayer board - 2S2P (2 signal, 2 power).
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NB7L86M
Table 8. DC CHARACTERISTICS (VCC = 2.375 V to 3.465 V, VEE = 0 V, TA = -40C to +85C)
Symbol ICC VOH VOL Vth VIH VIL VIHD VILD VCMR VID IIH IIL RTIN RTOUT RTemp Coef Characteristic Power Supply Current (Inputs and Outputs Open) Output HIGH Voltage (Notes 9 and 10) Output LOW Voltage (Notes 9 and 10) Input Threshold Reference Voltage Range (Note 11) Single-ended Input HIGH Voltage (Note 12) Single-ended Input LOW Voltage (Note 12) Differential Input HIGH Voltage Differential Input LOW Voltage Input Common Mode Range (Differential Configuration) Differential Input Voltage (VIHD - VILD) Input HIGH Current Input LOW Current Internal Input Termination Resistor Internal Output Termination Resistor Internal I/O Termination Resistor Temperature Coefficient D0/D0/D1/D1 SEL/SEL D0/D0/D1/D1 SEL/SEL VCC - 60 VCC - 460 1125 Vth + 75 VEE 1200 VEE 1163 75 0 0 -50 -50 45 45 50 20 50 20 50 50 6.38 Min Typ 38 VCC - 30 VCC - 400 Max 50 VCC VCC - 310 VCC - 75 VCC VCC - 150 VCC VCC - 75 VCC - 38 2500 150 150 100 100 55 55 Unit mA mV mV mV mV mV mV mV mV mV mA mA W W mW/C
Differential Input Driven Single-Ended (see Figures 16 & 18)
Differential Inputs Driven Differentially (see Figures 17 & 19)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. CML outputs require 50 W receiver termination resistors to VCC for proper operation. 10. Input and output parameters vary 1:1 with VCC. 11. Vth is applied to the complementary input when operating in single-ended mode. 12. VCMR min varies 1:1 with VEE, VCMR max varies 1:1 with VCC.
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NB7L86M
Table 9. AC CHARACTERISTICS (VCC = 2.375 V to 3.465 V, VEE = 0 V; Note 13)
Symbol Characteristic Min VOUTPP fdata tPLH, tPHL tSKEW tJITTER Output Voltage Amplitude (@VINPPmin) fin 4 GHz (See Figure 7) fin 8 GHz Maximum Operating Data Rate Propagation Delay to Output Differential @ 1 GHz (See Figure 7) Dx/Dx to Q/Q SEL/SEL to Q/Q 240 125 10.7 70 110 -40_C Typ 350 230 12 90 135 2.0 5.0 fin = 4 GHz fin =8 GHz fdata = 5 Gb/s fdata =10 Gb/s 75 Q, Q 0.2 0.2 2.0 4.0 400 35 120 180 10 20 0.5 0.5 8.0 10 2500 60 75 Max Min 240 125 10.7 70 110 25_C Typ 350 230 12 90 135 2.0 5.0 0.2 0.2 2.0 4.0 400 35 120 180 10 20 0.5 0.5 8.0 10 2500 60 75 Max Min 240 125 10.7 70 110 85_C Typ 350 230 12 90 135 2.0 5.0 0.2 0.2 2.0 4.0 400 35 120 180 10 20 0.5 0.5 8.0 10 2500 60 Max mV Gb/s ps Unit
Duty Cycle Skew (Note 14) Device-to-Device Skew (Note 15) RMS Random Clock Jitter (Note 16) Peak/Peak Data Dependent Jitter (Note 17)
ps ps
VINPP tr tf
Input Voltage Swing/Sensitivity (Differential Configuration) (Note 18) Output Rise/Fall Times @ 1 GHz (20% - 80%)
mV ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 13. Measured by forcing VINPP (TYP) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps (20% - 80%). 14. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw- and Tpw+ @1 GHz. 15. Device to device skew is measured between outputs under identical transition @ 1 GHz. 16. Additive RMS jitter with 50% duty cycle clock signal. 17. Additive peak-to-peak data dependent jitter with input NRZ data (PRBS 2^23-1). 18. VINPP (MAX) cannot exceed VCC - VEE. Input voltage swing is a single-ended measurement operating in differential mode.
500 OUTPUT VOLTAGE AMPLITUDE (mV) VCC - VEE = 3.3 V VCC - VEE = 2.5 V 300
400
200
100
0
0
1
2
3
4
5
6
7
8
9
10
11
12
INPUT FREQUENCY (GHz)
Figure 7. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fin) at Ambient Temperature (Typical)
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NB7L86M
Voltage (45 mV/div)
DDJ = 1.2 ps*
Voltage (45 mV/div)
DDJ = 1.2 ps*
Time (72 ps/div)
Time (72 ps/div)
Figure 8. Typical Output Waveform at 2.488 Gb/s with PRBS 2^23-1 (Vinpp = 75 mV)
*Input signal DDJ = 10 ps
Figure 9. Typical Output Waveform at 2.488 Gb/s with PRBS 2^23-1 (Vinpp = 400 mV)
Voltage (45 mV/div)
Voltage (45 mV/div)
DDJ = 2 ps**
DDJ = 2 ps**
Time (20 ps/div)
Time (20 ps/div)
Figure 10. Typical Output Waveform at 10 Gb/s with PRBS 2^23-1 (Vinpp = 75 mV)
**Input signal DDJ = 12 ps
Figure 11. Typical Output Waveform at 10 Gb/s with PRBS 2^23-1 (Vinpp = 400 mV)
Voltage (45 mV/div)
DDJ = 4 ps***
Voltage (45 mV/div)
DDJ = 4 ps***
Time (16 ps/div)
Time (16 ps/div)
Figure 12. Typical Output Waveform at 12 Gb/s with PRBS 2^23-1 (Vinpp = 75 mV)
***Input signal DDJ = 14 ps
Figure 13. Typical Output Waveform at 12 Gb/s with PRBS 2^23-1 (Vinpp = 400 mV)
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NB7L86M
D VINPP = VIH(D) - VIL(D) D Q Q tPHL tPLH VOUTPP = VOH(Q) - VOL(Q)
Figure 14. AC Reference Measurement
VCC
50 W Q Driver Device Q Z = 50 W Z = 50 W
50 W D Receiver Device D
Figure 15. Typical Termination for Output Driver and Device Evaluation (Refer to Application Note AND8020 - Termination of ECL Logic Devices)
D Vth Vth D
D
D
Figure 16. Differential Input Driven Single-Ended
Figure 17. Differential Inputs Driven Differentially
VCC Vthmax
VIHmax VILmax VIH Vth VIL VIHmin VILmin
VCC VCMmax VCMR D D VCMmax GND
VIHDmax VILDmax VID = VIHD - VILD VIHDtyp VILDtyp VIHDmin VILDmin
Vth
D Vthmin GND
Figure 18. Vth Diagram
Figure 19. VCMR Diagram
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NB7L86M
VCC
50 W
50 W Q Q
16 mA VEE
Figure 20. CML Output Structure
Table 10. INTERFACING OPTIONS
INTERFACING OPTIONS CML LVDS AC-COUPLED RSECL, LVPECL LVTTL, LVCMOS CONNECTIONS Connect VTD0, VTD0, VTD1, VTD1, VTSEL to VCC Connect VTD0, VTD0 together for D0 input. Connect VTD1, VTD1 together for D0 input. Leave VTSEL open for SEL input. Bias VTD0, VTD0, VTSEL and VTD1, VTD1 Inputs within (VCMR) Common Mode Range Standard ECL Termination Techniques. See AND8020/D. An external voltage should be applied to the unused complementary differential input. Nominal voltage 1.5 V for LVTTL and VCC/2 for LVCMOS inputs.
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NB7L86M
Application Information
All inputs can accept PECL, CML, and LVDS signal levels. The input voltage can range from VCC to 1.2 V.
VCC
Examples interfaces are illustrated below in a 50 W environment (Z = 50 W).
VCC
50 W
50 W
Q
Z VCC Z
D VTD 50 W NB7L86M
NB7L86M
Q VCC VEE
D VTD
50 W
VEE
Figure 21. CML to CML Interface
VCC
VCC
50 W PECL Driver Recommended RT Values VCC RT VEE VEE 5.0 V 290 W 3.3 V 150 W 2.5 V 80 W RT
Z VBIAS Z
D VTD 50 W NB7L86M D VBias VTD 50 W
50 W RT
VEE
Figure 22. PECL to CML Receiver Interface
VCC
VCC
Z LVDS Driver Z
D VTD 50 W NB7L86M D VTD 50 W
VEE
VEE
Figure 23. LVDS to CML Receiver Interface
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NB7L86M
ORDERING INFORMATION
Device NB7L86MMN NB7L86MMNG NB7L86MMNR2 NB7L86MMNR2G Package QFN-16 QFN-16 (Pb-Free) QFN-16 QFN-16 (Pb-Free) Shipping 123 Units/Rail 123 Units/Rail 3000 Tape & Reel 3000 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NB7L86M
PACKAGE DIMENSIONS
16 PIN QFN MN SUFFIX CASE 485G-01 ISSUE B
D A B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG DIM A A1 A3 b D D2 E E2 e K L SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.20 --- 0.30 0.50
PIN 1 LOCATION
0.15 C 0.15 C
0.10 C
16 X
0.08 C
16X
L
NOTE 5 4
16X
K
1 16 16X 13
0.10 C A B 0.05 C
NOTE 3
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
CCC CCC CCC
TOP VIEW (A3) SIDE VIEW D2
5
E
A A1
C 0.575 0.022
SOLDERING FOOTPRINT*
3.25 0.128 0.30 0.012
e
EXPOSED PAD
8
EXPOSED PAD
9
E2
12
e
3.25 0.128
1.50 0.059
b BOTTOM VIEW 0.50 0.02
0.30 0.012
SCALE 10:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NB7L86M/D

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